A memory cell of an NAND type EEPROM is shown in FIG. 28. FIG. 28 is a schematic sectional view of the memory cell MC. The gate insulation film GO which is formed between floating gate FG and channel region CA is sufficiently thin to allow an electron tunnel effect to occur between the floating gate FG and channel region CA is sufficiently thin to allow an electron tunnel effect to occur between the floating gate FG and the channel region CA. Electrons are emitted from the floating gate FG to the channel region CA by supplying a high voltage to the substrate Sb, and 0V to the control gate CG, so that one of a binary data is stored in the memory cell. On the other hand, when the other of a binary data is stored in the memory cell, electrons are injected from the channel region CA to the floating gate FG. In order to inject electrons to the floating gate FG, a high voltage is supplied to the control gate CG, and 0V is supplied to the channel region CA, source S and drain D. A part of a memory cell array of the NAND type EEPROM is shown in FIG. 29(a). The memory cells MC are serially connected between the select transistor ST and the transistor 10. Further, FIG. 29(b) shows voltage waveform diagrams at the respective nodes shown in FIG. 29(a). When data are programmed to the memory cells MC, first electrons are emitted from the floating gates FG of all the memory cells MC to the substrate by setting all the row lines WL1 to WLn connected to the control gates CG to 0 V and the substrate to a high voltage. After that, a high voltage is supplied to the row select line S connected to the gates of the select transistors ST connected to the memory cells MC to which data are to be written. At the same time, signal φ which is applied to the gates of the transistors 10 is set to 0 V to turn off transistors 10 to disconnect the memory cells MC from the reference potential VSS. When electrons are injected to the floating gates FG of the memory cells MC, the row line WL corresponding thereto is set to the high potential V1, and column lines D corresponding thereto are set to 0 V. At this time, a potential difference between the floating gates FG and the channel region CA becomes large enough to occur the electron tunnel effect, so electrons are injected to the floating gates FG from the channel region CA. On the other hand, the non-selected row lines WL are set to the potential V2 lower than the high potential V1. At this time, although the potential of the column lines D is 0 V, since the potential V2 is low, the potential difference between the floating gate FG of the memory cells applied the potential V2 and the channel region CA is not large enough to cause the electron tunnel effect, so electrons are not injected to the floating gates FG of the memory cells applied to the potential V2. In the memory cells connected to the row line WL of the high potential V1, if the column lines D are set to the potential V3, since the potential difference between the floating gates FG and the channel region CA is not large enough to cause the electron tunnel effect, electrons are not injected to the floating gates FG. In FIG. 29(b), at time T1 electrons are injected to the floating gate FG of memory cell 2n, but not injected into the floating gate FG of the memory cell 1n because the voltage of the column line D1 in the potential V3. In the same way, at time T2, electrons are injected to the floating gate FG of memory cell 11, but not injected to the floating gate FG of the memory cell 21.
In the memory cells MC, if the electrons are injected to the floating gate PG thereof, the threshold voltage thereof becomes a positive value; and if the electrons are emitted from the floating gate FG thereof, the threshold voltage thereof becomes a negative value. In a data read node, when the memory cell MC is selected, the gate thereof is set to a logic “0”, for instance to 0 V. When the threshold voltage of the selected memory cell MC is the negative value, the selected memory cell MC is turned on. However, when the threshold voltage of the selected memory cell MC is the positive value, the selected memory cell MC is turned off. The data stored in the selected memory cell MC is detected depending on whether or not the selected memory cell MC is turned on. On the other hand, the gate of the non-selected memory cell MC connected to the selected memory cell is set to a logic “1”, for instance to 5 V. So the non-selected memory cell MC is turned on even when electrons are injected into the floating gate.
Referring to FIG. 30, the data reading operation will be explained. The depletion type MOS transistor L1 which acts as a load for the memory cell, the select transistor (enhancement type) ST, the memory cells M1 to M8, and the transistor 10 are connected in series between the power supply voltage VDD and the reference potential (VSS). The gate of the transistor L1 is connected to a connecting point (node N1) between the transistor L1 and the select transistor ST. The signal K for selecting memory block 11 composed of the memory cells M1 to M8 is supplied to the gate of the select transistor ST. Further, the signals W1 to W8 for selecting one of the memory cell of the memory block 11 are supplied to the gates of the memory cells M1 to M8, respectively. The sense amplifier 12 is connected to the node N1. The date stored in the selected memory cell can be read by being detected the voltage level of the node N1 by the sense amplifier 12. In the data read node, the signal φ which is applied to the gate of the transistor 10 is a logic “1”. So the transistor 10 is turned on. The memory block 11 is connected to the reference potential through the transistor 10 in the data read mode. In the circuit shown in FIG. 30, the assumption is made that electrons are emitted from the floating gates of the memory cells M2 and M4, so the threshold voltages of the memory cells M2 and M4 are negative, and further the memory cell transistor M4 is selected, for instance. The threaded voltages of the other memory cells M1, M3, and M5 to M8 are positive. In this case, as shown by a timing chart in FIG. 31, the signal X is set to a logic “1”, the signals W1 to W3, W5 to W8 are set to a logic “1”, and the signal W4 is set to a logic “0”. By the above-mentioned setting, the select transistor ST and the memory cells M1 to M3 and M5 to M8 are turned on. Further, since the threshold voltage of the memory cell M4 is negative, this memory cell M4 is also turned on. Accordingly, the node N1 is discharged toward the reference potential through the select transistor ST, the memory cells M1 to M8, and the transistor 10. The data stored in the memory cell M4 can be read by being detected the voltage of the node N1 by the sense amplifier 12. After that, the memory cell M3 is assumed to be selected. In this case, the signal W3 is set to a logic “0”, and all other signals are set to a logic “1”. In this case, since the threshold voltage of the memory cell M3 is positive, the memory cell M3 is turned off. Thus, since the discharging path of the node N1 toward the reference potential is cut off, this node N1 is charged toward the power source voltage VDD through the transistor L1. By detecting the charged voltage of the node N1, the data can be read from the memory cell M3.
However, in the case where data of a logic “1” or a logic “0” is stored in the memory cell depending on whether the threshold voltage of the memory cell is negative or positive, the amount of current flowing through the memory blocks is according to the number of the memory cells having positive threshold voltage and the number of the memory cells having negative threshold voltages which are included in the memory block. So the amount of current flowing through each of the memory blocks is different from each other. Thus, the discharging speed at the node N1 differs according to the number of the memory cells whose threshold voltages are positive and the number of the memory cells whose threshold voltages are negative in the series-connected memory cells of the memory block.
For instance, as shown in FIG. 32(a), in the case where electrons are injected to the floating gates of the memory cells M1 to M7 so that these memory cells have a positive threshold voltage and further where only the memory cell M8 has a negative threshold voltage. If the memory cell M8 is selected, since the threshold voltages of all the other transistors M1 to M7 are positive, the amount of the currant flowing through the memory block 11 is a minimum. On the other hand, as shown in FIG. 32(b), in the case where all the memory cells M1 to M8 for constituting the memory block 11 have a negative threshold voltage, the amount of the current flowing through the memory block 11 is a maximum. Since the potentials of the signals W1 to W8 shown in FIG. 32(b) are the same as those shown in FIG. 32(a), a larger current flows through the memory cells whose threshold voltages are negative, compared with the memory cells whose threshold voltages are positive. Accordingly, in the NAND type EEPROM, there exist shortcomings in that the data read speed is determined depending on the ratio of the number of the memory cells having the positive threshold voltage to the number of the memory cells having the negative threshold voltage in the memory block, as described above. In addition, since the current flowing through the memory block of FIG. 32(a) is the minimum, it is necessary to determine the current driving capability of the load transistor L1 in accordance with the minimum current of the memory block, for this reason it is impossible to increase the current driving capability of the load transistor L1. Consequently, the charging speed at the node N1 is also lowered.
Furthermore, in the above-mentioned conventional memory device, one memory cell block corresponds to one column line. So, the area occupied by the memory cell array has been determined the junction portions between the memory cell blocks and the column lines at the two adjacent memory cell blocks. Further, the production yield has been influenced by an increase in the number of the column line wires and the number of the junction portions.
Further, one of a binary data are written by emitting electrons from the floating gates of all the memory cells at the same time to set the threshold voltages of the memory cells to the negative value. After that, the other of a binary data are written by selectively injecting electrons to the floating gates thereof.
When data are read from the memory cells, the selected row line is set to a logic “0” (e.g., 0 V) and the non-selected row lines are set to a logic “1” (e.g., 5 V). Since the non-selected row lines are at a logic “1”, the non-selected memory cells are turned on irrespective of whether the threshold voltages thereof are positive or not. On the other hand, the selected row line is at 0 V. Accordingly, if the threshold voltage of the selected memory cell is positive, the selected memory cell is turned off, and if the threshold voltage of the selected memory cell is negative, the selected memory cell is turned on. As already described above, the data stored in the memory cell is detected depending on whether the selected memory cell is turned on or off. The memory cell which has a positive threshold voltage is turned on if a logic “1” level signal is applied to the control gate thereof, and is turned off if a logic “0” level signal is applied to the control gate thereof. Therefore, care must be taken about the quantity of electrons injected into the floating gate. Accordingly, the injection of electrons and the reading for checking the quantity of electrons injected into the floating gate are carried out repeatedly, and the injection of the electrons is stopped whenever the threshold voltage of the memory cell reaches an appropriate value. However, since electrons are injected through an extremely thin gate insulation film, the threshold voltage of the memory cells after the injecting of electrons do not become uniform and vary according to a certain distribution owing to subtle variations in the quality of the gate insulation film and a manufacturing process. Thus, the threshold voltages of the memory cells in which electrons are injected are distributed within a range. Accordingly, a difference in the threshold voltage between the memory cell having the maximum threshold voltage and that having the minimum threshold voltage causes a difference in current flowing through the memory cell between the two, so that the data reading speeds from the selected memory cells differ according to the threshold voltages of the memory cells. In other words, since the current flows through the selected memory cell and the non-selected memory cells connected to the selected memory cell in series, the distribution of the threshold voltage of the non-selected memory cells causes directly the dispersion in the current flowing through the non-selected memory cells, so that the data read speed distributes according to the non-selected memory cells connected to the selected memory cell. To get a high data read speed, it is preferable to flow a large current through the memory cell. However, the threshold voltages of the memory cells in which electrons are injected must have a positive value. So, even if the threshold voltage of the memory cell having a minimum value is set to a value slightly higher than 0 V, the threshold voltage of the memory cell having a maximum value is inevitably a value far higher than 0 V due to the distribution of the threshold voltages of the memory cells in which electrons are injected.
In addition, in conventional NOR type flash EEPROM, when data is programmed, first, electrons are injected to the floating gates of all the memory cells to uniformalize the quantities of electrons stored in the floating gates of all the memory cells, and then electrons are emitted from the floating gates of all the memory cells. The other of a binary data is selectively written in the selected memory cell by applying a high voltage to the control gate and the drain of the selected memory cell to flow a channel current and thereby to inject electrons from the channel region to the floating gate of the selected memory cell. In the conventional NOR type flash EEPROM as described above, however, when electrons are emitted from the floating gate of the memory cell excessively, the threshold voltage of the memory cell becomes a negative value, so each non-selected memory cell whose gate voltage is set to 0V is rendered conductive, disabling a selecting operation. In the conventional NOR type flash EEPROM, therefore, the emitting of electrons and the reading of data of the memory cell are performed repeatedly, and the electron-emitted state of the floating gate is checked in each read operation so that the emitting of electrons is stopped when the threshold voltage of the memory cell reaches a proper value. To prevent electrons from being emitted excessively, a period of the emitting electrons is set to be short, and the emitting and the reading are repeated several times to obtain an appropriate threshold voltage. In this emitting of electrons, electrons are emitted from the floating gate to the source or drain of the memory cell by the electron tunnel effect, by applying 0 V to the control gate and a high voltage to the source or drain thereof. Accordingly, the thickness of the gate insulation film between the floating gate and the channel region is formed with an extremely, for example about 100 angstroms, so that the electron tunnel effect can be obtained. As a result, the threshold voltages of the memory cells obtained after electrons have been emitted are not uniform and thereby distribute within a range in all the memory cells, due to subtle variations in the manufacturing process. When the current flowing through the memory cell is large, the high data read speed is got. Accordingly, it is preferable that the threshold voltage of the memory cell is low. However, when electrons are emitted until an optimal threshold voltage can be obtained in the memory cell having the highest threshold voltage within the distribution, the threshold voltage of the memory cell having the lowest threshold voltage within the distribution becomes a negative value. To avoid this problem, in the EEPROM as described above, the threshold voltage of the memory cell having the lowest threshold voltage within the distribution is determined so as to become a positive value. Consequently, the data read speed of the memory cell having the highest threshold voltage within the distribution is delayed, and thereby it has been difficult to get a high date read speed.
FIGS. 33(a) to (d) show an example of the memory cell array of the conventional NOR type flash EEPROM, in which FIG. 33(a) is a plan view; FIG. 33(b) is a cross-sectional view taken along the line A–A′; FIG. 33(c) is a cross-sectional view taken along the line B–B′; and FIG. 33(d) is a cross-sectional view taken along the line C–C′. Further, FIG. 34 is a symbolic diagram thereof. In FIGS. 33(a) to (d), numeral 1 shows the row lines which form control gates of the memory cells. Numeral 2 shows the floating gates; 3 shows the channel regions; and 4 shows the gate insulation films. Numeral 5 shows the column lines formed of aluminum, for instance, which are connected to the drains 6 used in common for the two adjacent memory cells. Numeral 8 shows a wire formed of aluminum. For instance, for supplying a reference potential (e.g., a ground potential) when data are read and a high voltage when electrons are emitted from the floating gates, which is connected to source 7 of the memory cell at junction point 9 so as to be used in common for the two adjacent memory cells.
In the conventional nor type flash EEPROM constructed as described above, when electrons are emitted excessively from the floating gate and thereby the threshold voltage of the memory cell becomes a negative value, the non-selected memory cells whose control gates are at 0 V are turned on. Consequently, the column line 5 and the wire 8 are connected through the non-selected memory cell, so that current flows from the column line 5 to the wire 8 through the non-selected memory cell. Thus, when data are or written, even if a voltage is applied to the column line 5, since current flows through the non-selected memory cell, the applied voltage drops. Accordingly, even if the selected memory cell is turned off in the data read operation, since current flows through the non-selected memory cell, erroneous data are to be read and further it is impossible to supply a necessary and sufficient voltage in data writing. As a result, as already explained, in the dispersion range of all the memory cells after electrons have been emitted from the floating gates, since it is necessary to set the threshold voltage of the memory cell having the lowest threshold voltage to a positive value, the data read speed is determined by that of the memory cell having the highest threshold voltage, with the result that it is impossible to get a high data read speed.
As already explained, in the EEPROM, data are programmed by injecting and emitting electrons to and from the floating gates through the oxide film with a thickness of about 100 angstroms which is far thinner than that of the gate oxide film. FIG. 35 is a symbolic diagram showing a memory cell of a conventional EEPROM for programing data in further a different way. Here, the control gate voltage is showed by VCG; the drain voltage is showed by VD; the source voltage is showed by VS; and the drain current is showed by ID. The drain current ID relative to the control gate voltage VCG can be represented by the characteristics as shown in FIG. 36. In FIG. 36, curve A represents the initial characteristics; curve B represents the characteristics when electrons are injected to the floating gate, in which the threshold voltage is raised due to the injection of electrons; and curve C represents the characteristics when electrons are emitted from the floating gate, in which the threshold voltage change to negative due to the emission of electrons. In the memory cell, data of a logic “0” and a logic “1” are stored by use of the characteristics represented by the curves B and C.
FIG. 37 shows an example of the circuit configuration of the EEPROM constructed by arranging the memory cells as shown in FIG. 35 into a matrix pattern. As shown in FIG. 37, selecting MOS transistor ST is connected in series to memory cell transistor CT, and one memory cell 14 is composed of two transistors CT and ST. In the configuration as described above, when electrons are injected to the floating gate of the memory cell transistor CT, high voltages VG and VCG are applied to the gate of the selecting transistor ST and the control gate of the memory cell transistor CT, respectively, and in addition the column line 15 is set to 0 V. On the other hand, when electrons are emitted from the floating gate, the gate of the selecting transistor ST and the column line 15 are set to high voltages and the control gate of the memory cell transistor CT is set to 0 V. Thus, the high voltage is applied to the drain of the memory cell transistor CT, so that electrons are emitted from the floating gate to the drain.
FIG. 38(a) is a pattern plan view of region 16 enclosed by dot-dashed lines in the circuit shown in FIG. 37, and FIG. 38(b) shows a cross section taken along the line A–A′ in FIG. 38(a). In both FIGS. 38(a) and (b), the same reference numerals have been retained for the parts or elements corresponding to those shown in FIG. 37, and further the numeral 17 shows the source region of the memory cell transistors CT; 18 shows the drain of the memory cell transistor CT and the source region of the selecting transistor ST; 19 shows the drain region of the selecting transistor ST; 20 shows the floating gate of the memory cell transistor CT; 21 shows the control gate of the memory cell transistor CT; 22 shows the gate of the selecting transistor ST; 23 shows a thin gate insulation film; and 24 shows a contact portion between the column line 15 and the drain of the selecting transistor ST.
In the EEPROM as described above, in order to shorten the time required to program the data to the memory cells, as shown in FIG. 39, latch circuits L are provided for each column line 15. Further, data to be programmed to the memory cells 14 connected to the respective corresponding column line 15 are first latched by the latch circuits L respectively, and data are simultaneously programmed to the memory cells 14 for one row in accordance with the latched data of the latch circuit. In the EEPROM as constructed above, although it is possible to shorten the time required to program the data, since the latch circuits are provided for each column line, there exists a drawback in that the chip size increases to the extent required for the latch circuits, and thereby the chip cost increases.
In the semiconductor memory device already explained by FIGS. 28 to 32, the current flowing through the memory block differs according to the ratio of the number of the memory cells (constituting the memory block) having the positive threshold voltages to that having the negative threshold voltages. Accordingly, when the memory cells of the memory block include many MOS transistors having the positive voltages, the data read speed is delayed. In addition, since the current flowing through the memory block of FIG. 33(a) in the minimum, it is necessary to determine the current driving capability of the load transistor L1 in accordance with the minimum current of the memory block, for this reason it is impossible to increase the current driving capability of the load transistor L1. Consequently, the charging speed at the node N1 is also lowered.